Model 1707B Theory
SECTION IV
PRINCIPLES OF OPERATION
4-1. INTRODUCTION. 4-10. DELAY LINE.
4-11. The delay line provides approximately 160-11s
4-2. This section contains functional descriptions delay to the vertical signal, allowing the horizontal
keyed to an overall block diagram of the instrument, circuits sufficient time to react to the trigger signal
and simplified block diagrams of circuit groups. A so that the event caused by the trigger can be
detailed explanation of circuit functions, keyed to the observed on the fastest sweep.
schematics, is provided after the block diagram dis-
cussion. The schematics are located in Section VIII. 4-12. VERTICAL OUTPUT AMPLIFIER.
4-3. BLOCK DIAGRAM DISCUSSION. 4-13. The vertical output amplifier provides drive
to the CRT vertical deflection plates.
4-4. An overall explanation of circuit operation 4-14. TRIGGER CIRCUITS.
based on block diagrams (schematics 1 and 2) is pre-
sented to generate a basic understanding of the 4-15. The trigger assembly provides the main and
instrument. For simplicity, the block diagrams are delayed trigger signals to the integrators. Trigger
modes are selectable in this assembly. The main
drawn for function and do not show all circuit details.
trigger circuit provides two outputs to the main in-
tegrator (schematic 1). One output is the main
4-5. This instrument consists of a CRT, line
rectifier, gate assembly, and three modules. The trigger that is generated by the trigger gate driver.
The output of the trigger gate driver is controlled
modules are as follows: (1) vertical amplifier module by the inputs to the gated Schmitt trigger. One input
containing attenuators, vertical preamplifier, delay
1 to the gated Schmitt trigger is the trigger signal and
line, and vertical output amplifier; (2) a horizontal the other input is the reset signal from the main inte-
amplifier module containing trigger assembly, hori- grator. When the reset signal is high, the gated
zontal mother board, main and delayed integrators,
Schmitt trigger is inoperative and no trigger signal
main and delayed sweep time assemblies, holdoff is generated. When the reset signal is low, the gated
and comparator assembly, horizontal mode assembly,
horizontal preamplifier, and horizontal output ampli- Schmitt trigger is operational and a trigger signal
will be generated if there is an internal or external
fier; and (3) power supply module containing low trigger input. The other output is the bright-
voltage mother board, low voltage converter, low
line auto level which is provided only in the auto mode.
voltage rectifier and filter, high voltage oscillator, The delayed trigger circuit functions identically to the
and high voltage multiplier. main trigger circuit and provides a trigger signal
to the delayed integrator (schematic 12).
4-6. INPUT ATTENUATOR. (See schematic 1.)
4-16. MAIN INTEGRATOR.
4-7. The attenuators are compensated voltage-
divider types. They provide division ratios of 1, 2, 5,
10, and 100, giving nine separate sensitivities. Each 4-17. The main integrator initiates a horizontal
sweep from the trigger input. When the trigger signal
decade, input sensitivity range has an input capaci-
tance adjustment and an attenuator compensation is applied to the gate amplifier, the Miller integrator
adjustment. Coupling (AC, GND, and DC) is also activates and produces the horizontal sweep ramp.
The Miller integrator is connected to the main sweep
controlled in the attenuator stages.
timing components (schematic 11). The main TIME/
4-8. VERTICAL PREAMPLIFIER. DIV switch controls the ramp output from the Miller
integrator. The output of the Miller integrator is ampli-
4-9. The vertical preamplifier provides amplifi- fied and applied to the horizontal amplifier circuits.
cation to the input signals for drive to the vertical
output amplifier. Channel A sync and composite sync 4-18. The horizontal sweep is also compared to a 12-
signals originate in the vertical preamplifier. The volt reference by the ramp comparator which drives
sync signals are applied to the trigger assembly for in- the main integrator set-reset multivibrator. The set-
) ternal triggering. Channel switching, chop operation, reset multivibrator, in conjunction with the holdoff
and display mode are also accomplished in the ver- and comparator circuit, controls the amplitude and
tical preamplifier (schematic 7). timing sequence of the sweep ramp. When the
4-1 |
ACEC
